1. Field of the Invention
The present invention relates to the field of manufacturing of semiconductor devices, and, more particularly, to methods of manufacturing field effect transistors and methods for the formation of doped source and drain regions of field effect transistors.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are internally connected to form complex circuits, such as memory devices, logic devices and microprocessors. Improving the performance of integrated circuits requires reducing feature sizes. Besides allowing for an increase in operating speed due to reduced signal propagation delays, the reduced feature size makes it possible to increase the number of functional elements of the circuit, thereby increasing its functionality. Reducing the size of circuit elements, in particular reducing the size of field effect transistors, requires improved methods of manufacturing them.
A schematic cross-sectional view of a field effect transistor 1 is shown in FIG. 1. A substrate 2 comprises a doped active region 3. Shallow trench isolations 4, 5 isolate the active region 3 from neighboring circuit elements. An electrically conductive gate electrode 7 is formed over the substrate 2 and insulated from the substrate 2 by a gate insulation layer 6. The gate electrode 7 is flanked by sidewall spacers 12, 13. A source region 8 and a drain region 9 are adjacent to the sidewall spacers 12, 13. The field effect transistor 1 further comprises an extended source region 10 and an extended drain region 11 overlapping the source region 8 and the drain region 9. The extended source region 10 and the extended drain region 111 reach below the sidewall spacers 12, 13 and are adjacent to the gate electrode 7. The portion of the extended source region 10 which is not overlapped by the source region 8 is denoted as a source extension. Similarly, the portion of the extended drain region 11 which is not overlapped by the drain region 9 is denoted as a drain extension. The presence of the source/drain extensions allows better control of short channel effects.
A prior art process of manufacturing a field effect transistor is described with reference to FIG. 1. First, the trench isolations 4 and 5 and the active region 3 are formed within the substrate 2. Then, the gate insulation layer 6 and the gate electrode 7 are formed over the substrate 2 by well-known implantation sequences and deposition, photolithography and etch techniques, respectively. These formation processes are performed by means of advanced oxidation/deposition and photolithography techniques. Subsequently, the extended source region 10 and the extended drain region 11 are formed. This is done by implanting ions of a dopant material into the substrate 2. Portions of the substrate outside the transistor 1 which are not to be doped are photolithographically covered with a layer of photoresist which absorbs the ions. After implantation, the sidewall spacers 12, 13 are formed adjacent to the gate electrode 7 by deposition and anisotropic etch techniques. Then, the source region 8 and the drain region 9 are formed by ion implantation. The sidewall spacers 12, 13 protect the source extension and the drain extension from being irradiated with ions.
Ion implantation allows control of the distribution of dopants in the substrate. Dopant distribution can be controlled by varying the energy of the implant and/or the angle of incidence of the ions. The impact of energetic ions, however, leads to damage of the crystal lattice of the substrate. Ions lose energy through collision with substrate atoms. In these collisions, substrate atoms are pushed out of their positions in the crystal lattice, such that lattice defects, such as vacancies and interstitials, are created. Additionally, after ion implantation, the deposited dopants are not electrically active because they are sitting in interstitial sites instead of being incorporated into the crystal lattice of the substrate material.
Therefore, ion implantation is typically followed by annealing, which substantially repairs the substrate damages and activates the dopants. Frequently, this is done by rapid thermal annealing where the substrate is exposed to high temperature for a short time. Thus, source/drain regions with a low density of defects and dopant atoms sitting on sites in the crystal lattice of the substrate material are obtained.
Both the repair of lattice defects and the diffusion of dopant atoms in the substrate are thermally activated processes, the rate of which increases with temperature. Therefore, annealing also leads to an undesirable broadening of the distribution of dopant atoms in the substrate induced by dopant diffusion. If the substrate is exposed to temperature T for a time t, dopant atoms diffuse over a typical distance
d={square root over (2D(T)xc2x7t)}xe2x80x83xe2x80x83(1)
which is denoted as thermal budget. Here, D(T) is the diffusion constant of dopant atoms at temperature T. Since the diffusion constant of dopant atoms increases with temperature, the thermal budget increases as the annealing temperature T and the duration t of the annealing process increase.
If the size of field effect transistors is reduced, the thermal budget which can be tolerated is reduced, since, in smaller structures, only dopant diffusion over a shorter distance can be tolerated. This, in turn, restricts the possibility to heal lattice damage induced by ion implantation.
In view of the above-mentioned problem, a need exists for methods of manufacturing a field effect transistor which allow the creation of doped regions with a low density of lattice defects at a reduced thermal budget.
The present invention is generally directed to methods of manufacturing a field effect transistor where regions in the substrate are amorphized by implanting ions of a non-doping element prior to an annealing process.
According to one illustrative embodiment of the present invention, a method of manufacturing a field effect transistor comprises forming amorphized regions in an active region in a substrate by implanting ions of a non-doping element and forming source and drain regions with a specified lateral and depth profile in the amorphized region. The method further comprises performing a solid phase epitaxial regrowth of the amorphized regions at a temperature substantially maintaining the specified lateral and depth profile.
According to another illustrative embodiment of the present invention, a method of manufacturing a field effect transistor comprises forming an active region in a substrate, forming a gate electrode over the substrate, wherein the gate electrode is electrically insulated from the substrate by a gate insulation layer, and forming a first amorphized region and a second amorphized region in the substrate adjacent to the gate electrode by implanting ions of a non-doping element. The method further comprises forming a doped extended source region in the first amorphized region and a doped extended drain region in the second amorphized region by implanting ions of a first dopant, forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to the gate electrode, and forming a doped source region adjacent to the first sidewall spacer and a doped drain region adjacent to the second sidewall spacer by implanting ions of a second dopant. Finally, the method comprises annealing the substrate, which leads to solid phase epitaxial regrowth of the first and second amorphized regions, and to an activation of the first and second dopants.
According to another aspect of the present invention, a method of manufacturing a field effect transistor comprises forming an active region in a substrate, forming a gate electrode over the substrate, the gate electrode being electrically insulated from the substrate by a gate insulation layer, forming a doped extended source region and a doped extended drain region in the substrate adjacent to the gate electrode by implanting ions of a first dopant, and forming a first dielectric sidewall spacer and a second dielectric sidewall spacer adjacent to the gate electrode. The method further comprises forming a doped source region in the substrate adjacent to the first sidewall spacer and a doped drain region in the substrate adjacent to the second sidewall spacer by implanting ions of a second dopant and forming a first amorphized region comprising the extended source region and a second amorphized region comprising the extended drain region in the substrate by implanting ions of a non-doping element. Finally, the method comprises annealing the substrate, which leads to solid phase epitaxial regrowth of the first and second amorphized regions, and to an activation of the first and second dopants.